Script
Name
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Description
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bit2bus.pl
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Modifies
netlist to fix custom block instantiations and redefines bit
ports in to bus ports and removes the power and gnd port names
for custom blocks
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def2lef.pl
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Convert
Def to LEF file format
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def2.pl
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Converts
physical def file into a gate level verilog file format
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generate_stats.pl
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Generate
statistics from Synopsys rpt file using the -path end option
and generates AREA, TIMING HISTOGRAMS and WIRELOAD area report
is created
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spf2sdf.pl
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Convert
Spf generated from Silicon Ensemble to Sdf file format for
Synopsys
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hier_2_flat_sdf.pl
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Convert
Hier names to flat anmes in a SDF file for back
annotations.
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rspf_2_c_delay_calc.pl
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Modifies
the RSPF to feed into the Central Delay Calculator
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stitch_dspf.pl
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Stitches
dspf files together into a coherent whole.
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flatten_gate_level_verilog.pl
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Uses
Synopsys DC to Flatten a gate level verilog netlist
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merge_gds_text_file.pl
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Merges
text gds2 files from .strm format into a merged strm text file
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unique_def_components.pl
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Removes
all duplicate components in a DEF file, only the placed
ones are kept Eliminated duplicates are reported
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check_ports_conn.pl
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Check
IO ports Connectivity, unconnected ports are reported and also
a list of terminals for the source module
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split_timing_report.pl
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Split
timing reports from Synopsys rpt file into 3 files : .violate,
.unconstrained and .pass file.
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